Wednesday, June 20, 2012

in PSD – Silicon ( ASIC ) - Juniper Networks

Mr.Umesh Bhandare has been kind enough to forward this job offer for the benefit of fellow Swakula Salis.

Make maximum use of this and spread the word among fellow Salis.
While sending the resume, do send a cc to Mr.Umesh Bhandare. His email is

The Job offer goes like this….

Thanks for your continued support in making “ PARICHAY” successful !
In 2011, we hired about 40% of our new employees through “PARICHAY” – Juniper India’s employee referral program.

We look forward to receiving referrals for the below mentioned position in PSD – Silicon ( ASIC )

Please send in your referrals to with a CC to in WORD DOC format only.

Please do not “reply all” to this message.

Thanks and Regards,
Team “PARICHAY”- India Staffing Team

Position : ASIC Engineer / Staff
Role : Sr./Lead ASIC Design
Experience : 7+ years
Job Location: Bangalore

Job Summary
Lead design team to successfully complete block level/full chip design.
  • Develop micro-architecture and RTL implementation of large, complex high-speed ASIC’s for Juniper's next generation of networking products. 
  • Develop detailed micro architectural specification, RTL code, synthesis, closure on pre-layout timing, involve in PD activities to ensure first working silicon.
  • Develop module register specifications.
  • Need to make and maintain block schedule and complete tasks on or before time.
  • Work with verification engineers to close code coverage and ensure first-time working silicon.
  • Work with global physical design and signal integrity teams to achieve timing closure in routed netlists.
  • Mentor fresh graduate engineers with the design flow, strategy.

Position : ASIC Engineer / Staff
Role : Sr./Lead ASIC Verification
Experience : 8+ years
Job Location: Bangalore
Job Summary
Lead verification team to successfully complete block/chip/system level verification.
  • Perform ASIC verification for large, complex high-speed ASICs for Juniper's next generation of networking products.
  • Develop detailed test plans, block and system-level test benches and verification environments; achieve complete coverage to ensure first working silicon.
  • Develop functional models for System level architectural validation.
  • Lead ASIC and system bring-up. Lead a team of engineers to successfully deliver chip from specification to tape out.
  • Need to make and maintain schedule. Develop modelling/verification/coverage methodology.
  • work closely with logic designers, software developers. Mentor junior engineers with the verification flow, strategy.

Position: ASIC Engineer
Role: Physical Design Engineer
Location: Bangalore

Job Specification:

Work with internal Physical design teams and EDA vendors to develop and support ASIC physical design flow.  The position requires an overall understanding of the physical design flow from RTL to GDS.  The successful candidate will possess in-depth knowledge & experience in physical synthesis, design planning, floor planning, place & route, static timing analysis, and design closure & physical verification

·         Work with design to identify areas of flow improvement, develop plans and implement improvements.
·         Support ASIC design tools such as DC, ICC, Magma, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
·         Provide tool support and debug issues for & with members of design team.
·         Develop & maintain tool integration and productivity enhancement tools.
·         Develop and maintain a robust release mechanism for the distribution of the design environment.
·         Document & train designers on new methodology & flow usage.
·         Incorporate new tools to improve productivity into block level & full chip flow.
·         Test new features of tool and incorporate the new features when applicable.
·         Enhance current methodology to improve efficiency.
·         Will be responsible for all aspects of physical design for a block while developing methodology.

Qualification Requirements
·         4+ years of experience in physical design.
·         Experienced in design automation.
·         Understanding of timing constraints, SI prevention, power reduction.
·         Must have prior experience with place and route tools such as ICC. Magma and etc.
·         Must have worked on all aspects of physical design from placement to route, including extraction, timing, noise and EM IR analysis and fixes.
·         Must have completed design on 40nm and/or 28nm.
·         Proficient in Unix/TCL/Perl.
Good communication and presentation skills.  Requires good interpersonal skills and problem-solving ability.

What Juniper India ASIC offers?
ASIC Technology
  • 28 nanometer
  • 15-30 million placeable objects
  • 300 million gates
  • 2-5B transistors
  • 160 high speed links
  • Clock frequency – 640- 1000 MHz
Juniper ASIC team in Bangalore owns multiple major blocks / modules / chips across next generation...
  • Router
  • Switch
  • Data Center
  • Optical Chipset
Juniper ASIC
ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature rich without sacrifice in performance. Juniper ASIC Organizations mission is to deliver on-time, error-free, high performing, scalable, lowest cost, power efficient SILICON that is widely-deployable and beats the competition. We have developed 3 generations of high end router chipsets. ASIC was a differentiating factor for Juniper from our first product M40 to the latest T4000 and MX960. We have a track record of delivering 90+ ASIC’s, which were first time correct.

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1 comment:

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